1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device in which the potential of a selected word line in a static random access memory (static RAM) is changed according to the read mode and the write mode, whereby power dissipation can be reduced.
2. Description of the Prior Art
FIG. 6 is a schematic view showing a structure of a word line selecting system of a conventional static semiconductor memory device (CMOS static RAM). Referring to FIG. 6, a memory cell 3 comprises four transistors and two resistance elements. More specifically, the memory cell 3 comprises: n-MOS transistors Q3 and Q4, the drains and the gates thereof being cross-connected and the sources thereof being connected to a ground potential GND; an n-MOS transistor Q1, one conduction terminal thereof being connected to the drain of the transistor Q3, the other conduction terminal thereof being connected to a bit line (BL) 6 and the gate thereof being connected to a word line (WL) 5; and an n-MOS transistor Q2, one conduction terminal thereof being connected to the drain of the transistor Q4, the other conduction terminal thereof being connected to a bit line (BL) 7 and the gate thereof being connected to the word line (WL) 5. The drains of transistors Q3 and Q4 are connected to the power supply potential or voltage V.sub.cc through high resistance elements R1 and R2, respectively. The bit lines 6 and 7 are connected to the supply potential V.sub.cc through diode-connected load n-MOS transistors Q10 and Q11, respectively. The word line selecting system comprises x address decoders in two stages. The first x address decoder comprises a z decoder 1 formed by a NOR gate for receiving and decoding some of the x addresses and an inverter 10 for inverting an output signal received from the z decoder 1 to provide the inverted signal. The inverter 10 comprises complementally connected p-MOS transistor Q9 and n-MOS transistor Q8. More specifically, the gates of the transistors Q8 and Q9 are connected with each other to form an input portion of the inverter 10 and the drains of the transistors Q8 and Q9 are connected with each other to form an output portion of the inverter 10. The source of the transistor Q8 is connected to the ground potential GND and the source of the transistor Q9 is connected to the supply potential V.sub.cc. The output signal WLL of the inverter 10 is applied to the source of a p-MOS transistor Q7 to be described later and the complementary signal WLL of the inverter 10 is applied to the gate of the n-MOS transistor Q5, the drain of which is connected to the word line 5.
The second x address decoder comprises an x decoder 2 formed by a NAND gate for receiving and decoding the other x addresses and an inverter 20 for inverting a signal received from the x decoder 2 to provide the inverted signal to the word line 5. The inverter 20 comprises a p-MOS transistor Q7 and an n-MOS transistor Q6 which are complementarily connected. The gates of the transistors Q6 and Q7 are connected with each other to form an input portion of the inverter 20, through which the signal from the x decoder 2 is received. The drains of the transistors Q6 and Q7 are connected with each other to form an output portion of the inverter 20, through which the signal is provided to the word line 5. The source of the transistor Q7 receives the output signal WLL from the inverter 10 and the source of the transistor Q6 is connected to the ground potential GND.
The n-MOS transistor Q5 having the drain connected to the word line 5 is a transistor for pulling down the potential on the word line 5.
Now, the operation of the above described conventional device will be described. Consider the case in which all the x addresses are at the level "H". At this time, since the z decoder 1 and the x decoder 2 are both formed by the NAND gates, a signal at "L" is provided. Consequently, the output signal WLL of the inverter 10 coupled to the z decoder 1 is a signal at "H" with the supply voltage V.sub.cc level. On the other hand, the inverter 20 coupled to the x decoder 2 provides a signal at "H" to the word line 5 at this time as the signal WLL is applied to the source of the transistor Q7. At the same time, since the complementary signal WLL of the signal WLL is applied to the gate of the pull-down transistor Q5, the transistor Q5 is brought into the OFF-state and the word line selection signal WL on the word line 5 attains the level "H". Thus, the word line is selected.
In case where at least one signal of "L" is included in the x address signal, at least either the z decoder 1 or the x decoder 2 provides a signal of "H". Now consider the case in which the x decoder 1 provides a signal at "H". At this time, the output signal WLL of the inverter 10 becomes "L" and the output signal of the inverter 20 becomes "L" irrespective of the output signal level of the x decoder 2 (the signal WLL being applied to the source of the transistor Q7), and the level of the signal WL on the word line 5 becomes "L" in cooperation with the transistor Q5 brought into the ON-state. On the contrary, in case where the x decoder 2 provides a signal at "H", the inverter 20 provides a signal at "L" irrespective of the output signal level of the z decoder 1 and the signal WL on the word line 5 becomes "L".
The x decoder in a conventional static RAM is thus structured and with such structure, the word line selection signal WL can only take either the supply potential level V.sub.cc or the ground potential level GND. In the memory cell 3 connected to a selected word line, when the word line selection signal WL is at the level "H", electric current flows in the below indicated course. When the transistor Q3 is in the ON-state, electric current flows in the following circuit: power supply (V.sub.cc).fwdarw.transistor Q10.fwdarw.transistor Q1.fwdarw.transistor Q3.fwdarw.ground (GND). When the transistor Q4 is in the ON-state, electric current flows in the following circuit: power supply (V.sub.cc).fwdarw.transistor Q11.fwdarw.transistor Q2.fwdarw.transistor Q4.fwdarw.ground (GND). Thus, electric current flows in a large number of memory cells connected to a selected word line and as a result, the conventional semiconductor memory device involves a disadvantage that the amount of power dissipation is large.
Therefore, an object of the present invention is to provide a semiconductor memory device with reduced power dissipation, by which the above stated disadvantage can be overcome.